Field of the Invention
The invention relates generally to a last level cache controller and method for partitioning cache ways of a last level cache among processor cores.
Description of the Related Art
In multi-core computing system such as a heterogeneous computing system, shared last-level cache (LLC) management is critical to performance. Without proper management, massive memory accesses from one or more first cores (e.g., GPU cores) degrade the performance of one or more second cores (e.g., CPU cores). Cache partitioning is a commonly used technique for LLC management in such multi-core computing systems.
Several factors are important in performing LLC management. Firstly, latency-tolerant capability of GPUs needs to be taken into account. Secondly, cache resources are preferably allocated based on latency sensitivity (contribution of LLC access latency to the system performance) of each processor core. Thirdly, memory traffic incurred from less-sensitive cores may cause adverse effects on the overall performance because of prolonged off-chip access latency. As such, an efficient solution for LLC management that jointly considers the aforementioned factors is desired.